Memory System Design

In my career, I have worked with two computer architects who worked with Seymour Cray in designing supercomputers at Control Data Corporation and Cray Research.  To the best of my knowledge, those supercomputers used ultra-high-performance shared memory systems designed as described below.

These types of high performance memory systems can be designed using any type of memory component such as a memory chip or a disk drive.

Here's a single-bank memory system...


And here's a multiple-bank memory system...




Input and output multiplexers (muxes) can be added so that every input to the muxes can be connected to every output.  The muxes are digital switches that can be switched into any configuration almost instantaneously. 
 



Consider an initial switch configuration of the muxes as shown below...





Now consider switching the muxes at uniform intervals so that every set of input and output controllers are connected to every successive memory bank (modulo n+1) in successive time intervals.  For disk drives the time intervals would be fairly long to account for maximum access times.  For semiconductor memory chips, the time intervals would be short since access times are short.  The drawing below shows the second configuration of the muxes.  At the end of a mux cycle, the connections would return to the initial configuration above...




Now consider adding error-correcting code (ECC) encoders and decoders as shown below...




The memory banks are designed so that one ECC symbol is stored in one memory component so that one component failure only results in one ECC symbol failure per codeword.

The minimum amount of data that can be written or read in one time interval would be one codeword.  If the ECC code being used is a Hamming code, then each symbol is a bit and the minimum amount of data that could be written or read in one time interval is one Hamming codeword.

If the ECC code being used is a RS code, then the minimum amount of data that can be written or read in one time interval would be one RS codeword which is a set of nonbinary m-bit symbols from a finite field with 2m elements.

Most-likely future memory systems will be designed so that entire blocks of data are written or read in one time interval rather than single codewords and a 2D-RS error-correction scheme can then be used.

This type of a design results in very high performance since each controller has equal access to all of the memory banks and is guaranteed access within one mux cycle.  All of the memory banks can be busy all of the time resulting in the best possible performance.